1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a data input/output control circuit of the semiconductor memory device.
2. Description of the Prior Art
Semiconductor memory devices carry out write operations for transferring data received from the exterior of the device to a cell within the device, and execute read operations for transferring data within the cell to the exterior of the device. There is a tendency to share a write operation path and a read operation path in order to reduce the area of the device. There are various methods for controlling the path which shares the read and write operation.
With the demand for faster memory devices, at a frequency of 100 MHz or more, a data input/output line must operate within mere nanoseconds. Such an operation of the data input/output line has difficulty in repeating an operation for driving and precharging the data input/output within a few nanoseconds. Therefore, during the read operation, a current sense amplifier having a small swing (the voltage difference between a"high" level and a"low" level is a few millivolts) is used instead of utilizing a conventional method which fully swings the data input/output line between a power voltage and a ground voltage.
A conventional data input/output line is a shared line which always operates during the write and read operations, and when data is not written or read, for example, in case of not performing the write and read operations, in the middle of the successive write operation, and in the middle of the successive read operation. To exclude the possibility that there may occur an error due to the coupling or noise of effective data of the data input/output line, a latch is connected to the data input/output line.
Referring to FIG. 1, a conventional semiconductor memory device typically includes a cell 10, an input/output driver 12, a read driver 14, a signal PWT generating circuit 16, a write driver 18, a data output driver 20, and a latch 24. FIG. 2 illustrates the signal PWT generating circuit 16 shown in FIG. 1. The signal PWT generating circuit includes 6 serially connected inverters 40, 42, 44, 46, 48 and 50. FIG. 3 is an operational waveform chart of the semiconductor memory device of FIG. 1. The operation of the semiconductor memory device of FIG. 1 will now be described with reference to FIG. 3.
The signal PWT generating circuit 16 of FIG. 2 delays an input signal,"PCLK", and generates a signal PWT shown in FIG. 3. A precharge transistor 22 precharges a data input/output line,"DIO", in response to a precharge signal,"PRECH", shown in FIG. 3. The write driver 18 is enabled in response to a power signal PWR shown in FIG. 3, and passes input data,"DIN", to the data input/output line DIO in response to the signal PWT. The input/output driver 12 then transfers data received through the data input/output line DIO to the cell 10. The read driver 14 transfers data stored in the cell 10 to the latch 24 through the data input/output line DIO. The latch 24 holds data temporarily performing the write and read operations, in the middle of the successive write operation, and in the middle of the successive read operation. The data output driver 20 transmits data generated through the data input/output line DIO to the exterior.
The data write path of the conventional semiconductor memory device of FIG. 1 is: the signal PWT generating circuit 16 - the write driver 18 - the input/output driver 12 - the cell 10, and the data read path thereof is: the cell 10-the read driver 14-the data output driver 20. During writing, the input data DIN is transmitted to the data input/output line DIO through the write driver 18 at a"high" level of the signal PWT under the state that the power signal PWR and the precharge signal PRECH are at a"high" level.
When a current sense amplifier is used in case that there is the latch 24 as shown in the above semiconductor memory device, since the swing width of the data input/output line during the read operation is small, the latch can not be provided on the data input/output line. There are no problems even though the latch does not exist on the data input/output line during a read operation, since the current sense amplifier is used. However, a problem occurs during the write operation during the "floating interval" when the write driver is not transmitting the input data DIN onto the data input/output line. The floating interval varies with the input clock pulse width, according to the prior art. That is, in case that the successive write operation is implemented and a successive writing time interval varies, the writing time of the effective data is constant and the floating interval varies. However, as shown above, it would be desirable to keep the DIO line from floating too long yet avoid using a latch.